RISC-V Pipelined Processor Implementation

RISC-V Pipelined Processor Implementation

Python
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Overview

This project implements a 5-stage pipelined RISC-V processor that supports the RV64IM instruction set and D-extension for double-precision floating-point operations. It includes dedicated modules for instruction execution, memory handling, register operations, and floating-point arithmetic. The processor features hazard detection and forwarding mechanisms to handle data dependencies and maintain pipeline efficiency. Floating-point operations adhere to IEEE 754 standards, ensuring accurate computation. The modular design enhances maintainability, scalability, and performance across complex instruction sets.

Features

  • 64-bit RISC-V Processor
  • RV64IM and D-Extension Support
  • 5-Stage Pipeline
  • Hazard Detection and Forwarding Units
  • IEEE 754-compliant Floating-Point Operations
  • Structural Implementation of Arithmetic Units

Technical Details

Technical implementation details and architecture decisions.